Method for power routing and distribution in an integrated circuit with multiple interconnect layers

ABSTRACT

An integrated circuit  210  has a power grid formed from a first set of power buses  201   a  and  202   a  on a metal interconnect level M 1 , a second set of power buses  203   a  and  204   a  on interconnect level M 4 , and a third set of power buses  205   a  and  206   a  on inter-connect level M 5 . The set of power buses on level M 4  are oriented in the same direction as the set of power buses on level M 1 , and both sets of buses are located coincidentally. A high power logic cell  220  is pre-defined with a set of M 1 -M 4  power vias  221  and  222  so that logic cell  220  can be positioned in a horizontal row unconstrained by pre-positioned M 1 -M 4  power vias. Dummy cell  230  with M 1 -M 4  power vias is positioned as needed so as not to exceed a maximum strapping distance D 1 . A maximum value for distance D 1  is selected based on dynamic power requirements of nearby logic cells  250   a - n  as determined by simulation. A method for designing and fabricating integrated circuit  210  is described.

[0001] This application claims priority under 35 USC §119(e)(1) ofProvisional Application No. 60/073,018, filed Jan. 29, 1998.

FIELD OF THE INVENTION

[0002] This invention relates to integrated circuits, in particular tointegrated circuits that are designed using logic cells selected from acell library.

BACKGROUND OF THE INVENTION

[0003] Within an integrated circuit, complicated circuitry is generallyfashioned by interconnecting pre-designed cells that perform simplefunctions such as logic gates, latches, flip-flops, etc.; or morecomplex functions such as counters, registers, etc. Each cell must beconnected to power and ground, commonly referred to as Vdd and Vss, inorder to function.

[0004] In order to provide Vdd and Vss throughout the integratedcircuit, a power grid is defined which is fashioned from the variouslevels of conductive interconnects. Since the power grid is definedprior to laying out the integrated circuit, there are often conflicts inplacing the various cells that form the integrated circuit which resultsin a sub-optimum circuit layout.

[0005] An object of the present invention is to provide a dynamic powergrid construction methodology that allows optimum placement of thevarious cells that form an integrated circuit.

[0006] Other objects and advantages will be apparent to those ofordinary skill in the art having reference to the following figures andspecification.

SUMMARY OF THE INVENTION

[0007] In general, and in a form of the present invention a method fordesigning an integrated circuit which contains a number of high powerlogic cells, a number of low power logic cells and several interconnectlayers is provided. A power grid is defined which has a first set ofbuses on a first of the interconnect layers and a second set of buses ona second of the interconnect layers. Both sets of buses are orientedhorizontally and positioned approximately coincidentally. A layout ofthe integrated circuit is created by placing low power logic cells andhigh power logic cells in a horizontal row in such a manner that aposition along the row of each low power logic cell and each high powerlogic cell is not constrained by a pre-positioned power tap within thepower grid. Each low power logic cell is connected to a power bus in thefirst set of buses and each high power logic cell is connected to apower bus in the second set of buses.

[0008] In another form of the present invention, a third set of buses isplaced on a third of the interconnect layers and oriented in a verticalmanner. The third interconnect layer is place on top of the first twointerconnect layers and a set of interconnects are formed between thethird set of buses and the second set of buses. If there is a conflictbetween a logic cell and one of these interconnects, the interconnect isdeleted.

[0009] In another form of the present invention, a fourth and fifthinterconnect layer are used for routing signal interconnections betweenthe logic cells. The fourth and fifth interconnect layers are placedbetween the first and second interconnect layers.

[0010] In another form of the present invention, a low power grid isdefined which is sufficiently robust to supply power for the set of lowpower logic cells. A layout of the integrated circuit is created inwhich all of the logic cells are connected to the low power grid. Theintegrated circuit design is then simulated to determine dynamic powerrequirements of each logic cell. A power contour map is formed whichrepresents the location of logic cells which have a high dynamic powerrequirement. A high power grid is defined which covers high power areasof the integrated circuit and the high power logic cells are connectedto the high power grid.

[0011] Other embodiments of the present invention will be evident fromthe description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other features and advantages of the present invention willbecome apparent by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings, in which:

[0013]FIG. 1 is an illustration of a prior art power grid which utilizesfour metal interconnect layers;

[0014]FIG. 2A is a shark tooth diagram of the high power integratedcircuit fabricated according to prior art FIG. 1;

[0015]FIG. 2B is a shark tooth diagram of a high power integratedcircuit fabricated according to aspects of the present invention;

[0016]FIG. 3 illustrates a logic cell in relation to the power bus onmetal level 1, according to an aspect of the present invention;

[0017]FIGS. 4A and 4B are top and side views of an integrated circuitwith five interconnect layers and a power grid according to an aspect ofthe present invention;

[0018]FIG. 5 is a top view of a portion of an integrated circuit whichillustrates optimum packing of logic cells, according to an aspect ofthe present invention;

[0019]FIGS. 6A and 6B are top views of logic cells used in FIG. 5;

[0020]FIG. 7 is a dynamic power contour map of an integrated circuit,according to an aspect of the present invention;

[0021]FIG. 8 illustrates a power grid which does not take into accountdynamic power requirements;

[0022] FIGS. 9A-9C illustrate a power grid which does take into accountdynamic power requirements, according to an aspect of the presentinvention;

[0023]FIG. 10A-10B illustrate wider row spacing to accommodate widermetal spacing on first level metal in a power grid, according to anaspect of the present invention;

[0024]FIG. 11 illustrates variable strap spacing on second level metal,according to an aspect of the present invention;

[0025]FIG. 12 is a plot of utilization of various types of power gridoptimization from FIGS. 10A, 10B and FIG. 11 versus increasing powerrequirements;

[0026] FIGS. 13A-13E are shark tooth diagrams which illustrate theresult of utilizing the various power grid optimizations of FIG. 12;

[0027]FIG. 14 is a block diagram of an integrated circuit which isdesigned and fabricated according to aspects of the present invention;and

[0028]FIG. 15A is an illustration of a computer system which contains adesign program incorporating aspects of the present invention; and

[0029]FIG. 15B is a block diagram of the computer of FIG. 15A.

[0030] Corresponding numerals and symbols in the different figures andtables refer to corresponding parts unless otherwise indicated.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0031] Aspects of the present invention include methods for designingand fabricating an integrated circuit. In the following description,specific information is set forth to provide a thorough understanding ofthe present invention. Well known methods, circuits and devices areincluded in block diagram form in order not to complicate thedescription unnecessarily. Moreover, it will be apparent to one skilledin the art that specific details of these blocks are not required inorder to practice the present invention.

[0032] Integrated circuits are now generally designed by selectingpre-designed logic cells from a cell library and interconnecting theselected cells to form a final circuit. The circuit is laid out bypositioning each cell in a matrix and interconnecting the logic cells bymeans of various interconnect layers. A power grid provides power toeach logic cell. The power grid is generally defined first, asillustrated in FIG. 1, which is an illustration of a prior art powergrid which utilizes four metal interconnect layers. In FIG. 1, power buslines 100 a and 100 b are representative of a set of buses 100 a-n whichare on a first, or level 1, metal interconnect layer and are oriented ina horizontal direction. Likewise, power bus lines 101 a and 101 b arerepresentative of a set of buses 101 a-n which are also on the level 1metal interconnect layer. Bus lines 101 a-n are for a voltage Vdd, whilebus lines 100 a-n are for ground or Vss. Bus lines 102 a and 102 b arerepresentative of a set of buses 102 a-n on a second, or level 2, metalinterconnect layer which are oriented vertically. A set ofinterconnects, referred to as “vias” are placed in a regular patternbetween bus lines 102 a-n and bus lines 101 a-n as indicated by vias 110a-d. A similar set of level 2 buses and interconnects are provided forVss. A third set of power buses represented by bus lines 103 a and 103 bare placed on metal level 3 in a horizontal orientation and a fourth setof power buses represented by bus line 104 a and 104 b are placed on ametal level 4 in a vertical orientation. A set of vias represented byvias 111 a-d interconnect the level 2 bus lines and the level 3 buslines, while another set of vias represented by vias 112 a-dinterconnect the level 3 bus lines with the level four bus lines. Thus,a power grid is defined with buses oriented in a“horizontal-vertical-horizontal-vertical” (referred to HVHV) manner.Disadvantageously, the three sets of vias generally restrict placementof logic cells. For example, logic cells 120 a-n can be placed as shownunder bus lines 100 a and 101 a. However, logic cell 121 cannot beplaced in location 122 because of the presence of via 110 b. Therefore,logic cell must be placed as shown and the area within location 122 isessentially wasted. Also, it can be seen that a significant amount ofspace is required on metal level 2 and metal level three for powerbuses, which reduces the amount of space available for signal lineinterconnections between the logic cells.

[0033]FIG. 2A is a shark tooth diagram of the high power integratedcircuit fabricated according to prior art FIG. 1. Layers 151-155correspond to metal level 1 through metal level 5. Shaded area 160represents a percentage of the total area on level 1 that is used toroute signal lines within logic cells. Shaded areas 161 a-e represent apercentage of the area on each metal level that is dedicated to powerbuses. Shaded areas 162 a-e represent a percentage of area on each metallevel that is available for signal line routing. A significant portionof each metal layer is dedicated to power buses.

[0034]FIG. 2B is a shark tooth diagram of a high power integratedfabricated according to aspects of the present invention. Layers 151-155again correspond to metal level 1 through metal level 5. Shaded area 170represents a percentage of the total area on level 1 that is used toroute signal lines within logic cells. Shaded areas 171 a-e represent apercentage of the area on each metal level that is dedicated to powerbuses. Shaded areas 172 a-e represent a percentage of area on each metallevel that is available for signal line routing. An aspect of thepresent invention is that only a small percentage of metal level 2 andmetal level 3 is needed for power buses, advantageously leaving moreroom for signal line interconnects on metal layers which are closest tothe logic cells.

[0035]FIG. 3 illustrates a logic cell in relation to the power bus onmetal level 1, according to the present invention. Power bus line 201represents one voltage bus, typically referred to as Vdd or Vcc. Powerbus line 202 represent a second voltage bus, typically referred to asground or Vss. Power bus line 201 has a width W1 and power bus line 202has a width W2. W1 and W2 have approximately the same value.Alternatively, W1 and W2 may have different values in anotherembodiment. The dark line 200 a represent a boundary of a logic cell200. Various types of logic cells are pre-designed and stored in a celllibrary. A height H of each cell is a fixed value, for example 13.6 μm.A width W is variable to accommodate a variable number of transistors,depending on the logic function of the logic cell. Within boundary 200a, area on metal layer 1 that is not reserved for power bus lines 201and 202 can be used for inter-cell signal routing.

[0036]FIG. 4A and 4B are top and side views of an integrated circuit 210with five interconnect layers and a power grid formed on top of asubstrate 211 according to the present invention. For clarity, FIG. 4Aonly shows metal layer 1. A set of power buses, of which bus line 201and 202 are representative, are placed in metal layer 1 in a horizontalorientation. Various low power logic cells, such as logic cell 225 whichconforms to the logic cell of FIG. 3, are located in rows aligned withthe power bus lines, as described above. Various high power logic cells,such as logic cell 220 which also conforms to the logic cell of FIG. 3,are also located in the rows aligned with the power bus lines. Low powercells, such as low power cell 225, have contacts 226 and 227 whichcontact power bus lines 201 b and 202 b, respectively, to provide powerto cell 225. Referring to FIG. 4B, high power cells, such as high powercell 220, have contacts 223 and 224 which contact bus line 201 a and 201b, respectively, to provide power to cell 220. According to an aspect ofthe present invention, high power cell 220 also has a set of M1-M4 powervias 221 and 222 for contacting a second set of power bus lines 203 aand 204 a which are located on metal layer M4. M1-M4 power via 221 isformed from an M1-M2 vial 221 c, an M2-M3 via 221 b, and an M3-M4 via221 c and interconnecting metal segments on level M2 and level M3.

[0037] Still referring to FIG. 4B, five metal layers are shown as layerM1, layer M2, layer M3, layer M4 and layer M5. Each layer is separatedby a layer of insulation. The set of power bus lines, including buslines 201 a and 202 a, on layer M1 are oriented in a horizontal manner.According to an aspect of the present invention, the second set of powerbuses including bus lines 203 a and 204 a, on layer M4 are also orientedin a horizontal manner. Furthermore, each bus line on layer M4 islocated coincidentally above a corresponding bus line on layer M1, asshown by bus line 203 a for voltage Vdd directly above bus line 201 a,and bus line 204 a for voltage Vss directly above bus line 202 a. Athird set of power buses on layer M5, including power bus line 207 a,are oriented in a vertical manner. A set of M4-M5 power vias, 207 a-ninterconnect power bus line 205 a with each of power bus lines 203 a-n.Advantageously, a large percentage of the area of layer M2 and layer M3can be used for signal line interconnects between the various logiccells, as indicated by signal line 211 on layer M2 and signal line 212on layer M3. Note that the metal layer orientation stack-up is HVHHV.However, the orientation of layers M2 and M3 are not critical to thepresent invention. A stack-up of HHAVHV can also be used. Furthermore,more than two interconnect layers or less than two interconnect layerscan be placed between the first and second set of power buses on layersMl and M4 without affecting the novel aspects of the present invention.

[0038]FIG. 5 is a top view of a portion of integrated circuit 210 whichillustrates optimum packing of logic cells, according to an aspect ofthe present invention. FIG. 5 also illustrates a top view of a portionof the second set of power buses on level M4, and a portion of the thirdset of power buses on layer M5. Note that while bus line 203 a is shownto be adjacent to bus line 201 a in FIG. 5, this is for clarity only.Bus lines on layer M4 are coincident with corresponding bus lines onlayer M1, as indicated in FIG. 4B. Layer M5 is the top interconnectlayer, which allows the set of bus lines on layer M5 to be relativelywide and thick to increase current capacity, since planarization forsubsequent layers is not an issue.

[0039] Still referring to FIG. 5, a series of logic cells 241 a-n areplaced in a row corresponding to power bus lines 201 a and 202 a in acompacted manner so as not to waste area on integrated circuit 210.Logic cell 220 is advantageously placed directly next to logic cell 241n, even though logic cell 220 is in close proximity to vertical bus line206 a. Since there are no pre-positioned power vias between the firstset of power buses on layer M1 and the second set of power buses onlayer M4, the position of logic cell 220 is not constrained by M1-M4power vias. Furthermore, since the third set of power buses on level M5are wide, several M4-M5 power vias are located at each power bus signalintersection, as indicated by M4-M5 power vias 208 a-c. Advantageously,if there is a conflict between an M4-M5 power via and an M1-M4 power viawhich is included with a high power logic cell, then one or more M4-M5vias can be deleted without compromising the integrity of the powergrid. This is illustrated by power cell 220 which includes M1-M4 powervias 221 and 222. With a preferred placement of logic cell 220, aninterference occurs between power via 221 and an M4-M5 via site 207 c.Advantageously, M4-M5 via 207 c is deleted so that the placement of highpower logic cell 220 is not constrained by a pre-positioned power viawithin the power grid.

[0040] Still referring to FIG. 5, another aspect of the presentinvention will now be described. It is desirable to position an M1-M4power via at intervals along power bus lines 202 a and 204 a, forexample, at a distance that does not exceed a certain value for distanceD1. Distance D1 is determined so that current flowing in a segment ofpower bus 202 a on level Ml will not cause an excessive voltage drop dueto the resistance of that segment of power bus 202 a. A maximum valuefor D1 is also based on parameters for controlling electromigration ofmetal atoms in the segment of power bus. High power logic cell 220includes M1-M4 power via 222. As low power logic cells 250 a-n do notinclude an M1-M4 power via, a dummy cell 230 which contains only M1-M4power vias 231 and 232 is placed so that a maximum value for D1 is notexceeded. The maximum value for D1 is selected based on the averagecurrent requirement of low power logic cells, in general. Alternatively,the maximum value for D1 is selected based on the current requirementsof low power logic cells 250 a-n. Alternatively, the maximum value forD1 is selected based on the current requirements of logic cells on bothsides of dummy cell 230. Alternatively, the maximum value for D1 isselected based on the dynamic power requirements of nearby logic cells,as will be described later. Dummy cell 230 requires a minimal area whichis only large enough to accommodate vias 231 and 232. Alternatively,dummy cell 230 can be placed coincidentally with a low power logic cell,such as low power logic cell 225 in FIG. 4A in such a manner thatcontacts 226 and 227 form a portion of M1-M4 power vias 231 and 232 sothat no additional area is consumed by dummy cell 230.

[0041]FIGS. 6A and 6B are top views of logic cells used in FIG. 5. FIG.6A illustrates high power logic cell 220 with M1-M4 power via 221 forVdd, and M1-M4 power via 222 for Vss. FIG. 6B illustrates dummy cell 230with M1-M4 power via 231 for Vdd, and M1-M4 power via 232 for Vss.

[0042]FIG. 7 is a dynamic power contour map of an integrated circuit300, according to an aspect of the present invention. At any point inthe design process of an integrated circuit, dynamic power requirementsof the logic cells comprising the integrated circuit can be determinedby a number of simulation methods, such as those in the following list.Each of these methods or techniques has different accuracy andcomplexity considerations:

[0043] 1) output load of a logic cell based on load capacitance andaverage frequency;

[0044] 2) output load and internal load based on load capacitance andinternal cell capacitance and average frequency;

[0045] 3) output toggle count of a cell;

[0046] 4) output toggle count and time relationships from back annotatedsimulation;

[0047] 5) STA based cell output switch windows for possible simultaneousswitching considerations;

[0048] 6) post placement driver cell load based on Manhattan or globalinterconnect capacitance and load capacitance and average frequency.

[0049] This list is by no means exhaustive or restrictive to the presentinnovative aspects. The first five technique can easily identify cellsthat may have high power requirements. With this knowledge, they can beplaced in a manner that simplifies the power grid. Alternatively, M1-M4power vias can be added or deleted from a pre-designed logic cell, orlogic cells can be selected based on dynamic power requirements prior tocreating a trial layout for the integrated circuit. Method six involvescreating a trial layout of the integrated circuit, and then simulatingthe operation of the circuit using load capacitances which include thecapacitance of the signal interconnect lines. With any of the methods, acontour map can be created based on a trial layout and the dynamic powerrequirements determined by simulation. Such a map for integrated circuit300 is illustrated in FIG. 7, with high power areas 310, 311, and 312and low power areas 320, for example.

[0050]FIG. 8 illustrates a power grid for integrated circuit 300 whichdoes not take into account dynamic power requirements. Integratedcircuit 300 has five levels of metal interconnect. M1-M5. The top mostlayer M5 contains heavy power busing for power distribution that is notshown for clarity. Power bus lines on layer M5 or oriented horizontally.A uniform set of high power buses is provided on level M4 in a verticalorientation and a uniform set of high power buses is provided on levelM3 in a horizontal orientation. The various buses are interconnected asappropriate at intersections. A uniform set of low power buses is alsoprovided on levels M1 and M2, but not shown.

[0051] FIGS. 9A-9C illustrate a power grid for integrated circuit 300which does take into account dynamic power requirements, according to anaspect of the present invention. FIG. 9A illustrates level M5 with a setof heavy power buses 350 a-350 n which are selected to support theaverage power requirements of integrated circuit 300. In this figure,other layers are not shown, for clarity. As with FIG. 8, a uniform setof low power buses is also provided on levels M1 and M2, but not shown,which includes a set of M1-M2 power vias at intersections of the powerbuses on level M1 and level M2. A set of M2-M5 power vias are placed atintersections of power buses on level M2 and level M5. The low powerbuses are sufficiently robust to supply power for all low power cellsused in integrated circuit 300.

[0052] Prior to placing logic cells for integrated circuit 300, highpower cells are identified by simulation as described above andinstantiated with library cells which have M1-M3 power vias. A triallayout is then created by placing cells as described with reference toFIG. 3. After placement, a second simulation can be performed todetermine dynamic power requirements for each cell with regard toadditional loading provided by signal line interconnect capacitance, asdescribed above. High power cells are designated based on the simulationresults. A power contour map is formed based on the locations of thehigh power cells and high power areas, such as 310-312 are identified.

[0053]FIG. 9B illustrates level M4, with other layers removed forclarity. A set of buses 360 a-360 n are provided to cover only highpower areas 310-312; advantageously, buses 360 a-360 n are not providedin low power area 320. A set of M4-M5 power vias, not shown, areprovided at power bus line intersections of power bus lines on layer M4and the power bus lines on layer M5.

[0054]FIG. 9C illustrates level M3 and M4, with other layers removed forclarity. A set of buses 370 a-370 n are provided only in high powerareas 310-312. A set of M3-M4 power vias, not shown, are provided atpower bus line intersections of power bus lines on layer M3 and thepower bus lines on layer M4. Power bus lines 370 a-370 n are placedcoincidentally with the power bus lines on layer M1 so that the M1-M3power vias included in each high power logic cell make contact with oneof the power bus lines on layer M3.

[0055] FIGS. 10A-10B illustrate wider row spacing to accommodate widermetal spacing on first level metal in a power grid, according to anaspect of the present invention. FIG. 10A illustrates a portion of anintegrated circuit with a row of logic cells 400 and a second row oflogic cells 401. Each row of logic cells has a height H, as discussedwith reference to FIG. 3. Vdd power bus line 402 has a width WI and Vsspower bus line 403 has a width W2, also as discussed with reference toFIG. 3. Logic cell rows 400 and 401 are placed directly adjacent of eachother, such that a row to row spacing S1 has a value of approximately 0.In this embodiment, W1=W2=1.35 μm and H=13.6 μm.

[0056]FIG. 10B illustrates a portion of a different integrated circuitwith a row of logic cells 410 and a second row of logic cells 411. Eachrow of logic cells has a height H, as discussed with reference to FIG.3. Vdd power bus line 412 has a width W3 and Vss power bus line 413 hasa width W4, which are larger than W1 and W2 of FIG. 10B. Thisadvantageously increases the current capacity of power bus lines 412 and413. In this embodiment, W3=W4=2.2 μm. Logic cell rows 410 and 411 areplaced apart from of each other, such that row to row spacing S2 has avalue of approximately 1.7 μm to accommodate the wider power bus lines.

[0057] Other embodiments can have various values for W3, W4, and S2according to current requirements of respective logic cells. Also,within a single integrated circuit, power bus line widths can be madedifferent according to different power requirements for different rowsof logic cells. Row to row spacing is adjusted to accommodate the powerbus widths on a row by row basis.

[0058]FIG. 11 illustrates variable strap spacing on second level metal,according to an aspect of the present invention. As discussed withrespect to FIGS. 9A-C, a set of power buses on level M2 strap togetherthe set of power buses on level M1, and also interconnect withadditional power buses on higher layers, such as layer M5. It has beendetermined that the distance D2 between power bus lines on layer M2 canbe reduced from a preselected value to reduce the length of unstrappedmetal on layer Ml; thus, effectively reducing the amount of logic cellsand current on power bus lines on layer M1 between straps. Thepreselected value for D2 is 500 μm as a maximum value. It has beendetermined that distance D2 can be reduced in stages to as low as 130 μmbefore problems with logic cell placement and I/O port access intovarious logic cells becomes a serious problem. Thus, according to anaspect of the present invention, a complete circuit for an integratedcan be simulated to determine dynamic power requirements, and thendistance D2 is selected from the range of 130-500 μm to provide anoptimum power grid.

[0059]FIG. 12 is a plot of utilization of various types of power gridoptimization from FIGS. 5, 9A, 9B, 9C, 10A, 10B and FIG. 11 versusincreasing power requirements. After determining the power requirementsof a complete integrated circuit, preferably by simulation, thefollowing steps are performed:

[0060] step 1: if current requirements would produce unacceptable IRdrops in power bus lines on layer M1, reduce spacing D2 of power buslines on level 2 from 500 μm to 130 μm, as needed, as described withreference to FIG. 11, or reduce spacing D1 of M1-M4 power vias;

[0061] step 2A: if the minimum strap spacing of 130 μm is exceeded, thenincrease the width of the power bus lines on level Ml; and

[0062] step 2B: reset level M2 spacing D1 or D2 to the maximum value of500 μm, as described with reference to FIG. 5 and FIGS. 9A-9C;

[0063] step 3: if current requirements would still produce unacceptableIR drops in power bus lines on layer Ml, reduce spacing D2 of power buslines on level 2 or spacing D1 of M1-M4 power vias from 500 μm to 130μm, as needed;

[0064] step 4: if the minimum strap spacing of 130 μm is exceeded, thenadd power bus lines on levels M3 and M4, as discussed with reference toFIGS. 9A-9C.

[0065] FIGS. 13A-13E are shark tooth diagrams which illustrate theresult of utilizing the various power grid optimizations of FIG. 12.FIG. 13A illustrates a low power integrated circuit which has minimalpower busing on layer M1 and layer M2.

[0066]FIG. 13B illustrates a medium low power integrated circuit that isdesigned using step 1 of FIG. 12.

[0067]FIG. 13C illustrates a medium power integrated circuit that isdesigned using step 3 of FIG. 12.

[0068]FIG. 13D illustrates a high power integrated circuit that isdesigned using step 4 of FIG. 12, and FIG. 13E illustrates a very highpower integrated circuit that is also designed using step 4 of FIG. 12.

[0069]FIG. 14 is a block diagram of an integrated circuit 1 which isdesigned and fabricated according to aspects of the present invention.In microprocessor 1 there is shown a central processing unit (CPU) 10,data memory 22, program memory 23, peripherals 60 and an external memoryinterface (EMIF) with a direct memory access (DMA) 61. CPU 10 furtherhas an instruction fetch/decode unit 10 a-c, a plurality of executionunits, including an arithmetic and load/store unit D1, a multiplier M1,an ALU/shifter unit S1, an arithmetic logic unit (“ALU”) L1, a sharedmultiport register file 20 a from which data are read and to which dataare written. Decoded instructions are provided from the instructionfetch/decode unit 10 a-c to the functional units D1, M1, S1, and L1 overvarious sets of control lines which are not shown. Data are providedto/from the register file 20 a from/to to load/store units D1 over afirst set of busses 32 a, to multiplier M1 over a second set of busses34 a, to ALU/shifter unit S1 over a third set of busses 36 a and to ALUL1 over a fourth set of busses 38 a. Data are provided to/from thememory 22 from/to the load/store units D1 via a fifth set of busses 40a. Note that the entire data path described above is duplicated withregister file 20 b and execution units D2, M2, S2, and L2. Instructionsare fetched by fetch unit 10 a from instruction memory 23 over a set ofbusses 41. Emulation circuitry 50 provides access to the internaloperation of integrated circuit 1 which can be controlled by an externaltest/development system (XDS) 51. Test circuitry 52 contains controlregisters and parallel signature analysis circuitry for testingintegrated circuit 1. Microprocessor 1 is described completely inco-assigned patent application Ser. No. 09/012,813 (TI-25311) which isincorporated herein by reference.

[0070]FIG. 15A is an illustration of a computer system 1000 whichcontains a design program incorporating aspects of the presentinvention; and FIG. 15B is a block diagram of the computer of FIG. 15A.A design program which contains the steps for designing an integratedcircuit using a dynamically constructed power grid according to aspectsof the present invention, as described in the previous paragraphs, isstored on hard drive 1152. This design program can be introduced intocomputer 1000 via a diskette installed in floppy disk drive 1153, ordown loaded via network interface 1156, or by other means. The programis transferred to memory 1141 and instructions which comprise theprogram are executed by processor 1140. A dynamic power grid is definedand can be displayed on monitor 1004. A layout of an integrated circuitis created and displayed on monitor 1004. The design program includes asimulator for determining a power contour map of the integrated circuit.

[0071] Once an integrated circuit such as data processing device 1 isdesigned using the design program on computer system 1000, theintegrated circuit is fabricated according to the layout. Fabrication ofdata processing device 1 involves multiple steps of implanting variousamounts of impurities into a semiconductor substrate and diffusing theimpurities to selected depths within the substrate to form transistordevices. Masks are formed to control the placement of the impurities.Multiple layers of conductive material and insulative material aredeposited and etched to interconnect the various devices. These stepsare performed in a clean room environment.

[0072] A significant portion of the cost of producing the dataprocessing device involves testing. While in wafer form, individualdevices are biased to an operational state and probe tested for basicoperational functionality. The wafer is then separated into individualdice which may be sold as bare die or packaged. After packaging,finished parts are biased into an operational state and tested foroperational functionality.

[0073] An alternative embodiment of the novel aspects of the presentinvention includes additional power buses for additional voltages on anyof layers M1-M5.

[0074] Another embodiment of the novel aspects of the present inventionprovides power buses constructed in a dynamic manner on a portion of anintegrated circuit and power buses formed without regard to the novelaspects of the present invention in another portion of the integratedcircuit.

[0075] In another embodiment, referring to FIG. 4 Band FIG. 5, the setof power buses on level M4 are placed offset from the correspondingbuses on level M1, but still in a parallel manner.

[0076] In another embodiment, referring again to FIG. 4 Band FIG. 5, afourth set of power buses is included on level M3 to accommodateextremely high power requirements.

[0077] In another embodiment, referring to FIG. 3, FIG. 4A, FIG. 4B,FIG. 10A and FIG. 10B, power bus lines on level Ml are arranged in analternating manner so that a space between each row of logic cells canbe filled in to form a solid power line. For example, in FIG. 4A, powerline 201 a is for voltage Vdd. According to this aspect of the presentinvention, power line 202 b is also for voltage Vdd, so that a spacebetween power line 201 a and 202 b is filled in with conductive materialand a single power line is formed. In this embodiment, the position ofVdd and Vss contacts in each logic cell is selected based on which roweach logic cell instantiation is placed. For example, in FIG. 10A, ifpower bus lines 402 and 403 are for voltage Vdd, then logic cells in row401 have Vdd contacts at the top of the cell with Vss contacts at thebottom of the cell, and logic cells in row 400 have Vdd contacts at thebottom of the cell and Vss contacts at the top of the cell.

[0078] An advantage of the present invention is that a power grid for anintegrated circuit can be optimized based on dynamic power requirementsof the logic cells which form the integrated circuit. By optimizing thepower grid, more routing space is available for signal lineinterconnects so that a complex circuit design can be routed tocompletion, or the size of the integrated circuit can be reduced.

[0079] As used herein, the terms “applied,” “connected,” and“connection” mean electrically connected, including where additionalelements may be in the electrical connection path.

[0080] While the invention has been described with reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various other embodiments of theinvention will be apparent to persons skilled in the art upon referenceto this description. It is therefore contemplated that the appendedclaims will cover any such modifications of the embodiments as fallwithin the true scope and spirit of the invention.

What is claimed is:
 1. A method for fabricating an integrated circuitwhich contains a plurality of high power logic cells, a plurality of lowpower logic cells and a plurality of interconnect layers, the methodcomprising the steps of: defining a power grid comprising a firstplurality of power buses on a first interconnect layer oriented in ahorizontal manner and a second plurality of power buses on a secondinterconnect layer oriented in a horizontal manner, such that the secondplurality of buses are positioned approximately coincidentally with thefirst plurality of buses; creating a layout of the integrated circuit byplacing a first portion of the plurality of low power logic cells and afirst portion of the plurality of high power logic cells in a horizontalrow in such a manner such that a position along the row of each lowpower logic cell and each high power logic cell is not constrained by apre-positioned power via within the power grid; connecting each lowerpower logic cell in the first portion to a first power bus in the firstplurality of power buses on the first interconnect layer; connectingeach high power logic cell in the first portion to a second power bus inthe second plurality of power buses on the second interconnect layer;and fabricating the integrated circuit according to the layout of theintegrated circuit.
 2. The method of claim 1, further comprisingselecting the plurality of low power logic cells and the plurality ofhigh power logic cells from a cell library which has a plurality oftypes of logic cells, comprising at least one high power logic celltemplate and at least one low power logic cell template, wherein eachhigh power logic cell template includes a power via for connecting toone of the second plurality of power buses on the second interconnectlayer.
 3. The method of claim 2, wherein the power via within each highpower logic cell template also connects to one of the first plurality ofpower buses on the first interconnect layer.
 4. The method of claim 3,further comprising placing a plurality of dummy power via cells selectedfrom the cell library in the first horizontal row to augment the firstportion of high power logic cells in such a manner that a pre-selectedpower via distance is not exceeded.
 5. The method of claim 3, wherein atleast one of the plurality of dummy power via cells is placedcoincidentally over an existing low power logic cell.
 6. The method ofclaim 4, wherein the step of defining a power grid further comprisesdefining a third plurality of power buses on a third interconnect layeroriented in a vertical manner, wherein the third interconnect layer isplaced in a topmost position with regard to the plurality ofinterconnect layers and interconnected with the second plurality ofbuses.
 7. The method of claim 6, further comprising: defining a set ofsecond to third power vias which interconnect the third plurality ofpower buses with the second plurality of buses; and deleting one or moreof the set of second to third power vias which interfere with apreferred placement location of the first plurality of high power cells,such that a position along the row of each low power logic cell and eachhigh power logic cell is not constrained by the set of second to thirdpower vias within the power grid.
 8. The method of claim 7, wherein thestep of creating a layout further comprises: routing signalinterconnections among the plurality of high power logic cells and theplurality of low power logic cells on a fourth interconnect layer and ona fifth interconnect layer; and locating the fourth interconnect layerand the fifth interconnect layer between the first interconnect layerand the second interconnect layer.
 9. A method for fabricating anintegrated circuit which contains a plurality of logic cells, a portionof which form a plurality of low power logic cells, and a plurality ofinterconnect layers, the method comprising the steps of: defining afirst power grid comprising a first plurality of power buses which issufficiently robust to supply power for the plurality of low power logiccells; creating a layout of the integrated circuit in which theplurality of logic cells are connected to the first power grid;simulating operation of the integrated circuit to determine a dynamicpower requirement of each logic cell in the plurality of logic cells;designating a portion of the plurality of logic cells as a plurality ofhigh power logic cells in response to the step of simulating, anddesignating a remaining portion of the plurality of logic cells as theplurality of low power logic cells; forming a power contour maprepresentative of the plurality of high power logic cells which has atleast one high power area; defining a second power grid comprising asecond plurality of power buses only in the high power area; connectingeach high power logic cell to the second plurality of power buses; andfabricating the integrated circuit according to the layout of theintegrated circuit.
 10. The method of claim 9, further comprisingidentifying a portion of the plurality of logic cells which have a highstatic power requirement as a portion of the plurality of high powerlogic cells.
 11. A method for designing an integrated circuit whichcontains a plurality of high power logic cells, a plurality of low powerlogic cells and a plurality of interconnect layers, the methodcomprising the steps of: defining a power grid comprising a firstplurality of power buses on a first interconnect layer oriented in ahorizontal manner and a second plurality of power buses on a secondinterconnect layer oriented in a horizontal manner; creating a layout ofthe integrated circuit by placing a first portion of the plurality oflow power logic cells and a first portion of the plurality of high powerlogic cells in a horizontal row in such a manner that a position alongthe row of each low power logic cell and each high power logic cell isnot constrained by a pre-positioned power via within the power grid;connecting each lower power logic cell in the first portion to a firstpower bus in the first plurality of power buses on the firstinterconnect layer; and connecting each high power logic cell in thefirst portion to a second power bus in the second plurality of powerbuses on the second interconnect layer.
 12. The method of claim 11,further comprising selecting the plurality of low power logic cells andthe plurality of high power logic cells from a cell library which has aplurality of types of logic cells, comprising at least one high powerlogic cell template and at least one low power logic cell template,wherein each high power logic cell template includes a power via forconnecting to one of the second plurality of power buses on the secondinterconnect layer.
 13. The method of claim 12, wherein the power viawithin each high power logic cell template also connects to one of thefirst plurality of power buses on the first interconnect layer.
 14. Themethod of claim 13, further comprising placing a plurality of dummypower via cells selected from the cell library in the first horizontalrow to augment the first portion of high power logic cells in such amanner that a pre-selected power via distance is not exceeded.
 15. Themethod of claim 13, wherein at least one of the plurality of dummy powervia cells is placed coincidentally over an existing low power logiccell.
 16. The method of claim 14, wherein the step of defining a powergrid further comprises defining a third plurality of power buses on athird interconnect layer oriented in a vertical manner, wherein thethird interconnect layer is placed in a topmost position with regard tothe plurality of interconnect layers and interconnected with the secondplurality of buses.
 17. The method of claim 16, further comprising:defining a set of second to third power vias which interconnect thethird plurality of power buses with the second plurality of buses; anddeleting one or more of the set of second to third power vias whichinterfere with a preferred placement location of the first plurality ofhigh power cells, such that a position along the row of each low powerlogic cell and each high power logic cell is not constrained by the setof second to third power vias within the power grid.
 18. The method ofclaim 17, wherein the step of creating a layout further comprises:routing signal interconnections among the plurality of high power logiccells and the plurality of low power logic cells on a fourthinterconnect layer and on a fifth interconnect layer; and locating thefourth interconnect layer and the fifth interconnect layer between thefirst interconnect layer and the second interconnect layer.
 19. A methodfor designing an integrated circuit which contains a plurality of logiccells, a portion of which form a plurality of low power logic cells, anda plurality of interconnect layers, the method comprising the steps of:defining a first power grid comprising a first plurality of power buseswhich is sufficiently robust to supply power for the plurality of lowpower logic cells; creating a layout of the integrated circuit in whichthe plurality of logic cells are connected to the first power grid;simulating operation of the integrated circuit to determine a dynamicpower requirement of each logic cell in the plurality of logic cells;designating a portion of the plurality of logic cells as a plurality ofhigh power logic cells in response to the step of simulating, anddesignating a remaining portion of the plurality of logic cells as theplurality of low power logic cells; forming a power contour maprepresentative of the plurality of high power logic cells which has atleast one high power area; defining a second power grid comprising asecond plurality of power buses only in the high power area; andconnecting each high power logic cell to the second plurality of powerbuses.
 20. The method of claim 19, further comprising identifying aportion of the plurality of logic cells which have a high static powerrequirement as a portion of the plurality of high power logic cells. 21.A computer system programmed with a method for designing an integratedcircuit which contains a plurality of high power logic cells, aplurality of low power logic cells and a plurality of interconnectlayers, the method comprising the steps of: defining a power gridcomprising a first plurality of power buses on a first interconnectlayer oriented in a horizontal manner and a second plurality of powerbuses on a second interconnect layer oriented in a horizontal manner;creating a layout of the integrated circuit by placing a first portionof the plurality of low power logic cells and a first portion of theplurality of high power logic cells in a horizontal row in such a mannerthat a position along the row of each low power logic cell and each highpower logic cell is not constrained by a pre-positioned power via withinthe power grid; connecting each lower power logic cell in the firstportion to a first power bus in the first plurality of power buses onthe first interconnect layer; and connecting each high power logic cellin the first portion to a second power bus in the second plurality ofpower buses on the second interconnect layer.
 22. The method of claim21, further comprising selecting the plurality of low power logic cellsand the plurality of high power logic cells from a cell library whichhas a plurality of types of logic cells, comprising at least one highpower logic cell template and at least one low power logic celltemplate, wherein each high power logic cell template includes a powervia for connecting to one of the second plurality of power buses on thesecond interconnect layer.
 23. A mass storage device containing aprogram for a method for designing an integrated circuit which containsa plurality of high power logic cells, a plurality of low power logiccells and a plurality of interconnect layers, the method comprising thesteps of: defining a power grid comprising a first plurality of powerbuses on a first interconnect layer oriented in a horizontal manner anda second plurality of power buses on a second interconnect layeroriented in a horizontal manner; creating a layout of the integratedcircuit by placing a first portion of the plurality of low power logiccells and a first portion of the plurality of high power logic cells ina horizontal row in such a manner that a position along the row of eachlow power logic cell and each high power logic cell is not constrainedby a pre-positioned power via within the power grid; connecting eachlower power logic cell in the first portion to a first power bus in thefirst plurality of power buses on the first interconnect layer; andconnecting each high power logic cell in the first portion to a secondpower bus in the second plurality of power buses on the secondinterconnect layer.
 24. The method of claim 23, further comprisingselecting the plurality of low power logic cells and the plurality ofhigh power logic cells from a cell library which has a plurality oftypes of logic cells, comprising at least one high power logic celltemplate and at least one low power logic cell template, wherein eachhigh power logic cell template includes a power via for connecting toone of the second plurality of power buses on the second interconnectlayer.
 25. An integrated circuit, comprising: a plurality of high powerlogic cells formed on a semiconductive substrate; a plurality of lowpower logic cells formed on the substrate; a first plurality of powerbuses on a first interconnect layer oriented in a horizontal mannerconnected to each of the plurality of low power logic cells and to eachof the plurality of high power logic cells; a second plurality of powerbuses on a second interconnect layer spaced above the first interconnectlayer oriented in a horizontal manner connected to each of the pluralityof high power logic cells, wherein the second plurality of buses ispositioned approximately coincidentally with the first plurality ofbuses; and a plurality of signal interconnect layer positioned betweenthe first interconnect layer and the second interconnect layer, whereinthe plurality of signal interconnect layers have no power buses.